Timing Performance of Nanometer Digital Circuits Under Process Variations by Victor Champac & Jose Garcia Gervacio

Author:Victor Champac & Jose Garcia Gervacio
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

(4.11)

where is the correlation between the distributions of the parameters W 1 and W 2, σ W1 is the standard deviation of W 1, and σ W2 is the standard deviation of W 2. The first term is the variance of the Nand delay due to variations only in W 1, the second term is the variance of the Nand delay due to variations only in W 2, and the third term is the covariance between the delay distributions due to W 1 and W 2.

Fig. 4.62-Nand gate. (a) Schematic circuit. (b) Layout

Since the transistors in the layout of a small cell (Fig. 4.6b) are usually very close, it can be assumed that the correlated variations impact similarly to the devices of a Nand gate [40, 41]. As a consequence, the distributions of W1 and W2 can be assumed fully correlated (). Replacing this condition in Eq. (4.11) and using delay sensitivities, the variance of the Nand delay due to the correlated parameters W 1 and W 2 is written as

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